NajahNow | MainPage
course not found

FPGA Digital Design Diploma


  • السعر  
      3500 جنيه
  • السعر لغير المصريين  
      240 دولار $
  • مدة الحاضرة  
      240 دقيقة
  • المدة  
      83 ساعة
  • تاريخ البدأ  
      2022-02-05
معلومات عن الكورس
Course Description: The goal of this course is to make any student don’t have experience or knowledge in digital design & FPGA, to be experienced in Digital electronics flow techniques using field programmable gate arrays (FPGAs). We will discuss FPGA architecture, digital design flow using FPGAs & Verilog coding guidelines. The course study will involve lab projects to give students hands-on experience on designing basic digital blocks, and implement & debug complex design applications as video processing, machine learning, etc.… using FPGAs. We will discuss timing violations and analyze power using ISE & Vivado IDE on Sparten-6 Board & Zynq-7000 FPGA Development kit. Target audience & Pre-requisites: • Students or Engineers having knowledge in Digital logic and familiar with any programming language like c. Course duration: • 12 days (48 hours – 4 hours per day – online). • 5 days (35 hours – 7 hours per day – onsite). • Total: 17 days (83 hours) Course Objectives After completing this course, you will be able to: ➢ Verilog Knowledge • How Verilog fits into the FPGA or ASIC design flow • How to use the Verilog language for hardware design and logic synthesis • How to write thorough Verilog text fixtures to verify your designs • How to avoid common mistakes when coding Verilog for synthesis ➢ HDL Synthesis and Implementation on FPGA • Use ISE IDE to create FPGA project on Sparten-6 development Kit. • Describe the Digital design flows in the industry. • Use the ISE IDE I/O Planning layout to perform pin assignments. • Synthesize and implement the HDL design. • Apply clock and I/O timing and physical constraints. • Implementing Digital design systems using Verilog HDL. • Be Familiar with Architecture of FPGA and basic elements of FPGA. • Basic Digital Design Concepts. • Practical practice on real implementation of combinational and sequential circuits runtime on FPGA ➢ Acceleration FPGA Design • Use ISE IDE to create FPGA project on Sparten-6 development Kit. • Use the New Project Wizard to create a new Vivado IDE project. • Describe the supported design flows of the Vivado IDE. • Generate a DRC report to detect and fix design issues early in the flow. • Use the Vivado IDE I/O Planning layout to perform pin assignments. • Synthesize and implement the HDL design with multiple options. • Apply clock and I/O timing constraints and perform timing analysis. • Use the Vivado logic analyzer and debug flows to debug a design. • Describe and use the clock resources in a design. • Identify synchronous design techniques. • Build resets into your system for optimum reliability and design speed. • Apply timing exception constraints in a design as part of the Baselining procedure to fine tune the design. • Create and package your own IP and add to the Vivado IP catalog to reuse. • Use the Vivado IP integrator to create a block design. • Debug a design with multiple clock domains with the help of multiple debug cores using the Vivado logic analyzer. • Describe how Power Analysis is done. • Apply baseline constraints to determine if internal timing paths meet design timing objectives. • Use Vivado Design Suite reports and utilities to full advantage, especially the Clock Interaction report.1

كورسات أخري للمدرس

كورسات أخري للسنتر
FPGA Digital Design Diploma
Eng. Omar Amin Mohamed
NajahNow
Egypt