تفاصيل الحجز

Description: Verification is all about analyzing, reviewing, and reporting anomalies in static work products. Includes, requirements, design, code, flowchart, manuals …. etc. Course Objective: The main aim of the course is to qualify students to have knowledge about the roles of the verification engineer in the market. The course gives a quick overview on the verification process in general and trains the applicant on how to construct a robust verification plan. After finishing the course, applicants shall be able to construct a verification plan and create complex testcases using UVM to test complex SoC designs. Corse Content and Schedule: • Verification basics o Session1-Verification basics • System Verilog o Session 2-Data types & process blocks o Session 3-Hierarchical structures o Session 4-compiler directives, scheduling, and assignments o Session 5-Classes o Session 6-Randomization o Session 7-Coverage • UVM o Session 8-UVM overview, UVM hierarchy, and base classes o Session 9-UVM Factory & phasing o Session 10-Resources and Configurations o Session 11-TLM o Session 12-Sequences and sequencers o Session 13-Components o Session 14-Full environment o Session 15-UVM testing Lab Course Prerequisite: • Basic knowledge of digital design • Good Knowledge of Verilog Hardware Description Language (HDL) is a must • Basic knowledge of verification flow is a plus • Basic knowledge of System Verilog is a plus1