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Digital Design for FPGA ISE R5


  • السعر  
      1500 جنيه
  • السعر لغير المصريين  
      100 دولار $
  • مدة الحاضرة  
      240 دقيقة
  • المدة  
      24 ساعة
  • تاريخ البدأ  
      2021-08-13
معلومات عن الكورس
Course Description: The goal of this course is to introduce digital design techniques using field programmable gate arrays (FPGAs). We will discuss FPGA architecture, digital design flow using FPGAs & Verilog coding guidelines. The course study will involve lab projects to give students hands-on experience on designing basic digital blocks on Sparten-6 Board using ISE IDE. Pre-requisites: • Knowledge of digital circuits • Basic HDL Knowledge (Verilog or VHDL) • Course Objectives • After completing this course, you will be able to: • Use ISE IDE to create FPGA project on Sparten-6 development Kit. • Describe the Digital design flows in the industry. • Use the ISE IDE I/O Planning layout to perform pin assignments. • Synthesize and implement the HDL design. • Apply clock and I/O timing constraints. • Implementing Basic elements in Digital design systems. • Be Familiar with Architecture of FPGA Course Contents: Day 1 • Introduction to FPGA Architecture, 3D IC, SoC. {Lecture}. • UltraFast Design Methodology Introduction. {Lecture}. • Top-Down Digital Design Flow {Lecture}. • Quick Review of Digital Systems Design {Lecture}. • Design of Combinational and Sequential Circuits Using Verilog. {Lecture}. Day 2 • Writing a Test Bench for the Design. {Lecture} • Digital Coding Guidelines. {Lecture}. • Synthesis and Implementation. {Lecture, Lab}. • Design of Memories. {Lecture}. Day 3 • Arithmetic Circuit Designs {Lecture}. • Frequency Divider {lecture}. • FSM {lecture, lab}. Day 4 • Review of FSM {lab}. • Introduction to Clock Constraints {Lecture, Lab}. • Setup and Hold Timing Analysis {Lecture}. • Debug Cores {Lecture}. Day 5 • Generate Bit-stream flow on FPGA {Lecture, Lab}. • UART Design Implementation of FPGA {Lecture, Lab}. • Final project Description {Lecture, Lab}. Time line course: The FPGA Course Period: 24 hours (4 hours per Session)1

كورسات أخري للسنتر
Digital Design for FPGA ISE R5
Eng. Omar Amin Mohamed
NajahNow
Egypt