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Verification in A Nutshell Course Course Objectives The main aim of the course is to qualify students to have knowledge about the roles of the verification engineer in the market. The course gives a quick overview on the verification process in general and trains the applicant on how to construct a robust verification plan. After finishing the course, applicants shall be able to construct a verification plan and create complex testcases using UVM to test complex SoC designs. Course Contents • Verification basics • System Verilog Session 1-Data types & process blocks Session 2-Hierarchical structures Session 3-compiler directives, scheduling, and assignments Session 4-Classes Session 5-Randomization Session 6-Coverage • UVM Session 1-UVM overview, UVM hierarchy, and base classes Session 2-UVM Factory & phasing Session 3-Resources and Configurations Session 4-TLM Session 5-Sequences and sequencers Session 6-Components Session 7-Full environment Session 8-UVM testing Lab Course Requirements • Basic knowledge of digital design • Knowledge of Verilog Hardware Description Language (HDL) is a must • Basic knowledge of verification flow is a plus • Basic knowledge of System Verilog is a plus1