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Vivado FPGA for Digital design and Embedded Systems R3


  • السعر  
      1550 جنيه
  • السعر لغير المصريين  
      950 دولار $
  • مدة الحاضرة  
      240 دقيقة
  • المدة  
      28 ساعة
  • تاريخ البدأ  
      2021-05-01
معلومات عن الكورس
Course Description: The goal of this course is to give the students that have digital design basics to implement and debug complex designs applications as video processing, machine learning, etc.… using FPGAs. We will discuss timing violations and analyze power using Vivado IDE. The course study will involve lab projects to give students hands-on experience on designing complex digital systems and Introduction to FPGA Design for Embedded Systems on Zynq-7000 FPGA Development kit. Pre-requisites: • Basics of FPGA. (Must) • Good HDL knowledge & practice. (Verilog is preferred) • Digital design knowledge & experience. • 7 days (39 hours – [5 hours per day-> online], [7 hours per day-> onsite]). What do I gain? ■ Programmable system integration • Follow UltraFast Design Methodology guidelines ■ Increased system performance. • Basic Constraints Usage • I/O Constraints and Virtual Clocks • Path-specific timing constraint usage • Create custom IP and package it to reuse • Use the HLx design flow to increase the productivity ■ Use the Power Estimator to identify resources that use power more efficiently than CLB logic. ■ Debug tools and cores do not consume any I/O pins. ■ learn and Implement basic video processing application. ■ learn and Implement high speed communication protocol interface on FPGA Course Objectives After completing this course, you will be able to: • Use the New Project Wizard to create a new Vivado IDE project. • Describe the supported design flows of the Vivado IDE. • Generate a DRC report to detect and fix design issues early in the flow. • Use the Vivado IDE I/O Planning layout to perform pin assignments. • Synthesize and implement the HDL design with multiple options. • Apply clock and I/O timing constraints and perform timing analysis. • Use the Vivado logic analyzer and debug flows to debug a design. • Describe and use the clock resources in a design. • Identify synchronous design techniques. • Build resets into your system for optimum reliability and design speed. • Apply timing exception constraints in a design as part of the Baselining procedure to fine tune the design. • Create and package your own IP and add to the Vivado IP catalog to reuse. • Use the Vivado IP integrator to create a block design. • Debug a design with multiple clock domains with the help of multiple debug cores using the Vivado logic analyzer. • Describe how Power Analysis is done. • Apply baseline constraints to determine if internal timing paths meet design timing objectives. • Use Vivado Design Suite reports and utilities to full advantage, especially the Clock Interaction report. • Be familiar how to create project using TCL scripts. Course Contents: Day 1 (online) • FPGA Architecture, 3D IC, SoC. {Lecture} • UltraFast Design Methodology Introduction. {Lecture} • Vivado Design Flows. {Lecture}. • Vivado Design Suite Project-Based Mode. {Lecture, Lab, Demo}. • Synthesis and Implementation. {Lab, Demo}. • Timing Constraints Wizard & Editor. {Lecture, Lab, Demo} • Clock Constraints. {Lecture, Lab, Demo} Day 2 (online) • Vivado Design Rule Checks. {Lab, Demo} • Setup and Hold Timing Analysis. {Lecture} • I/O Constraints and Virtual Clocks. {Lecture, Lab, Demo} • Vivado Timing Reports. {Lecture, Demo} • Vivado IP Flow. {Lecture, Lab, Demo} • Xilinx Power Estimator Spreadsheet. {Lecture, Lab, Demo} • Register Duplication. {Lecture} Day 3 (online) • Resets. {Lecture, Lab, Demo} • Generated Clocks. { Lecture} • Clock Group Constraints. { Lecture} • Timing Exceptions. {Lecture, Lab, Demo} • Creating and Packaging Custom IP. {Lecture, Lab, Demo} Day 4 (online) • Designing with IP Integrator. {Lab,Demo} • Case Study: Designing the AXI MPMC Using the IPI.{ Lecture} • Sampling and Capturing Data in Multiple Clock Domains. {Lecture, Lab, Demo} • Synchronization Circuits. {Lecture ,Lab,Demo} • HLx Design Flow. {Lecture, Lab, Demo} • Project Details. {Lecture} Day 5 (online) • Report Clock Interaction. {Lecture} • Baselining.{Lecture , lab, Demo} • Pipelining. {Lecture, Lab, Demo} • Inference. {Lab, Demo} • Project Discussion. Day 6 (onsite) • Project Test. Day 7 (onsite) • Project Testing and Implementation Instructor LinkedIn profile: https://www.linkedin.com/in/omar-amin-005a/1

كورسات أخري للمدرس

كورسات أخري للسنتر
Vivado FPGA for Digital design and Embedded Systems R3
Eng. Omar Amin Mohamed
NajahNow
Egypt