تفاصيل الحجز

Course Description: The goal of this course is to introduce digital design techniques using field programmable gate arrays (FPGAs). We will discuss FPGA architecture, digital design flow using FPGAs & Verilog coding guidelines. The course study will involve lab projects to give students hands-on experience on designing basic digital blocks on Sparten-6 Board using ISE IDE. Pre-requisites:  Knowledge of digital circuits  Basic HDL Knowledge (Verilog or VHDL) Course duration:  6 days ( 25 hours – 4 hours per day – 5 hours onsite) Course Objectives After completing this course, you will be able to:  Use ISE IDE to create FPGA project on Sparten-6 development Kit.  Describe the Digital design flows in the industry.  Use the ISE IDE I/O Planning layout to perform pin assignments.  Synthesize and implement the HDL design.  Apply clock and I/O timing and physical constraints.  Implementing Basic elements in Digital design systems using Verilog HDL.  Be Familiar with Architecture of FPGA. Course Contents: Day 1 (online)  Introduction to FPGA Architecture, 3D IC, SoC. {Lecture}.  UltraFast Design Methodology Introduction. {Lecture}.  Top-Down Digital Design Flow {Lecture}.  Quick Review of Digital Systems Design {Lecture}.  Design of Combinational and Sequential Circuits Using Verilog. {Lecture}. Day 2 (online-Verilog Day)  Introduction to Verilog. {Lecture}  Modules. {Lecture}  Nets and Values. {Lecture}  Formatting, Timescale. {Lecture}  Always Blocks. {Lecture}  Procedural Statements. {Lecture}  Clocks and Flipflops. {Lecture}  Operators and Parameters. {Lecture} Day 3 (online)  Writing a Test Bench for the Design. {Lecture}  Basic Digital Design concepts. {Lecture}  Digital Coding Guidelines. {Lecture}.  Synthesis and Implementation. {Lecture}. Day 4 (online)  FSM {lecture, lab}.  Frequency Divider {lecture}.  Project Description. [UART Design Implementation of FPGA] Day 5 (online)  Review of FSM {lab}.  Design of Memories. {Lecture}  Debug Cores. {Lecture}  Introduction to Constraints. {Lecture, Lab}  Demo for creating project files. {Lab} Day 6 (onsite)  UART Implementation on Spartan-6 FPGA. {Lab onsite}1