تفاصيل الحجز

Course Goals: Students who complete this course successfully will be able to go through all place and route steps and subjected to them practically: Day 1: Introduction (.lib files, NLDM, lef, technology lef. Synopsys Milkyway database, overall design flow) Day2: Basics of STA, Timing paths, FF basic requirements, timing Constraints. Day3: Synopsys tools design objects, Logic Synthesis, Formal verification, tutorial on Synthesis Day4: Floorplanning, power planning, placement, ICC tutorial1 Day5: CTS, Routing, Chip finishing, ICC tutorial 2 Day6: Complete tutorial (Synthesis, Formal verification, PnR, STA) Day7: Extraction and STA Day8: EMIR, Power Estimation Required Texts. Materials, or Equipment: • All will be supplied during the course Daily Work / Homework Project description could be as follow "RTL to GDSII Project: Going through digital design flow starting from Constraint translation from system level to TCL level, Synthesis, PnR steps, Timing Signoff and Physical verification, making sure to meet timing, power and physical specifications until design is clean to be fabricated "Course Policies and Information for Students The student must have attended the theoretical sessions before the practical / hands on sessions." Also, they should have good knowledge of HDL languages such as VHDL / Verilog.1